Integrated circuits (sets of transistors interconnected by electrical wires on a flat semiconductor piece) are the building blocks of virtually all electronic devices that exist today. Over the past 60 years, the relentless miniaturization of integrated circuits has led to an unprecedent increase in the ability to store and process information. Yet, this trend is now facing a serious roadblock [1]: as integrated circuits become smaller, the ever-increasing electrical resistivity of standard copper interconnects hampers the circuit performance, for example through the generation of heat.  

The theoretical reason for the increased resistivity of metallic wires upon reduction of their dimension was unveiled and quantified by K. Fuchs and E. Sondheimer in the first half of the 20th century [2,3]. The underlying intuition behind their theory is that in thinner wires, electrons carrying the current inside the wire encounter the rough surfaces of the wire more frequently. Such diffusive scattering leads to an increase in the wire’s resistivity.

The recent advent of topological materials has opened a gate to circumventing the aforementioned unfavorable resistivity scaling [4]. These materials are characterized by a set of nonzero integer numbers, known as topological invariants, which capture the topology of their electronic structures. In contrast, conventional materials, such as copper and silicon, have zero topological invariant. Generally, nonzero topological invariants manifest themselves physically through the appearance of robust metallic states at the surface of the material. These states provide a parallel surface conduction channel in addition to the conventional bulk conduction.

As the wire is made narrower, the contribution from the surface electrons to the wire’s average three-dimensional resistivity decreases linearly with the wire diameter, because the two-dimensional current density of the surface states is insensitive to the wire dimension. This scaling behavior is opposite to that of bulk electrons considered by Fuchs and Sondheimer. Now, the overall resistance of two resistors connected in parallel is determined mainly by the smaller resistance.  Thus, if the surface contribution to the current becomes dominant over the bulk contribution, the resistivity scaling established by Fuchs and Sondheimer is reversed.

A recent experiment on a topological semimetal [5] provides an illustration of the preceding discussion. This experiment reported that the room-temperature resistivity of the ~100 nm scale Weyl semimetal NbAs drops more than tenfold below its bulk resistivity to ~ 1μΩ cm, becoming even better than bulk copper. If the observed low resistivity persisted to the nanometer scale in semimetals compatible with silicon technologies, then replacing such a topological material for Cu in transistor wiring would boost the power-performance of integrated circuits by at least 10% to ~40%, equivalent to the performance gain of 1 to 4 technology-node generations. This implies that developing topological semimetal interconnects could have a disruptive impact to the semiconductor industry.

Nevertheless, the existing theoretical literature only reports resistivity scaling in toy Weyl semimetal models. There is no scaling study on broad classes of topological semimetals down to the ultrathin limit. Thus, we do not know if resistivity improves with reduced dimensions in all topological semimetals at all relevant length scales.  Also notably, due to the complexity and problem size, we are yet to find any scaling study for realistic materials using first-principles  band structure calculations. Thus, the industry lacks well-founded guidelines to help screen these materials for their adoptions.

 In our paper [https://www.nature.com/articles/s41535-022-00535-6], we address both needs. First, we introduce a new method that extends the first-principles based transport calculations to systems on the order of 50 nm (more than a tenfold improvement over the state-of-the-art in system size), validated against our analytical framework. Second, using this method, we obtain the resistivity scaling for a slab of topological semimetal, CoSi, that is compatible with silicon technology (see Fig. 1).

Fig. 1: (a) Unit cell of topological semimetal CoSi; (b) Electronic structure of a semi-infinite CoSi crystal. The bulk states are depicted in blue, while the surface states are shown in red.

Fig. 2: Resistivity  of a CoSi slab as a function of the slab thickness, calculated from first-principles, for different surface defect density N  ( N=0.01 is equivalent to a defect density ~ 5 x 10¹² cm^-2 ). In region I, well-differentiated surface and bulk states coexist at the Fermi level. In region II, only remnants of the surface states are present at the Fermi level. The resistivity in the infinite thickness limit is denoted as ρ₀. 

Our work presents three key findings (see Fig. 2):

1. There exists a critical sample thickness (2.7 nm, in CoSi) that divides the scaling trends. The critical thickness marks the entry of the bulk electronic bands at the Fermi energy, below which the surface states completely dominate transport.
2. Scaling above the critical thickness is determined by the ratio of surface-conductivity vs. bulk-conductivity. In samples with strong surface disorder, bulk conductivity dominates, and resistivity scaling reverts to that of conventional metals. In sufficiently clean samples where surface-state conductivity dominates, resistivity decreases with reduced feature size. This is novel and highly desirable for interconnect applications.
3. Most significantly, below the critical thickness, CoSi retains remnants of conducting surface states and shows decreasing resistivity with reduced sample thickness down to the ultrathin limit, in sharp contrast to both the topological insulators (where the surface states are fully gapped, and the system becomes more resistive) and conventional metals.

Our findings put the prospect of using topological semimetals for ultra-scaled interconnects on a firm theoretical basis, and provide guidelines for screening and engineering topological semimetals for interconnect applications.

[1] D. Gall, J. Appl. Phys. 127, 050901 (2020).

[2] K. Fuchs, Math. Proc. Cambridge Philos. Soc 34, 100 (1938).

[3] E. H. Sondheimer, Adv. Phys. 1, 1 (1952).

[4] See e.g. P. Liu, J. R. Williams and J. J. Cha, Nat. Rev. Matter. 4, 479 (2019).

[5] C. Zhang et al., Nat. Mater. 18, 482 (2019).